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424 lines
6.6 KiB
Go
424 lines
6.6 KiB
Go
// Inferno utils/6c/6.out.h
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// https://bitbucket.org/inferno-os/inferno-os/src/master/utils/6c/6.out.h
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//
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// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
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// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
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// Portions Copyright © 1997-1999 Vita Nuova Limited
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// Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com)
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// Portions Copyright © 2004,2006 Bruce Ellis
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// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
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// Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others
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// Portions Copyright © 2009 The Go Authors. All rights reserved.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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package x86
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import "github.com/twitchyliquid64/golang-asm/obj"
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const (
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REG_NONE = 0
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)
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const (
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REG_AL = obj.RBaseAMD64 + iota
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REG_CL
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REG_DL
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REG_BL
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REG_SPB
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REG_BPB
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REG_SIB
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REG_DIB
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REG_R8B
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REG_R9B
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REG_R10B
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REG_R11B
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REG_R12B
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REG_R13B
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REG_R14B
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REG_R15B
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REG_AX
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REG_CX
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REG_DX
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REG_BX
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REG_SP
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REG_BP
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REG_SI
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REG_DI
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REG_R8
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REG_R9
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REG_R10
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REG_R11
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REG_R12
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REG_R13
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REG_R14
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REG_R15
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REG_AH
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REG_CH
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REG_DH
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REG_BH
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REG_F0
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REG_F1
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REG_F2
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REG_F3
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REG_F4
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REG_F5
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REG_F6
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REG_F7
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REG_M0
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REG_M1
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REG_M2
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REG_M3
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REG_M4
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REG_M5
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REG_M6
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REG_M7
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REG_K0
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REG_K1
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REG_K2
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REG_K3
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REG_K4
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REG_K5
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REG_K6
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REG_K7
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REG_X0
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REG_X1
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REG_X2
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REG_X3
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REG_X4
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REG_X5
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REG_X6
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REG_X7
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REG_X8
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REG_X9
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REG_X10
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REG_X11
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REG_X12
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REG_X13
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REG_X14
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REG_X15
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REG_X16
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REG_X17
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REG_X18
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REG_X19
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REG_X20
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REG_X21
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REG_X22
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REG_X23
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REG_X24
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REG_X25
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REG_X26
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REG_X27
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REG_X28
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REG_X29
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REG_X30
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REG_X31
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REG_Y0
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REG_Y1
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REG_Y2
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REG_Y3
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REG_Y4
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REG_Y5
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REG_Y6
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REG_Y7
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REG_Y8
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REG_Y9
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REG_Y10
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REG_Y11
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REG_Y12
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REG_Y13
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REG_Y14
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REG_Y15
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REG_Y16
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REG_Y17
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REG_Y18
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REG_Y19
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REG_Y20
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REG_Y21
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REG_Y22
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REG_Y23
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REG_Y24
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REG_Y25
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REG_Y26
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REG_Y27
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REG_Y28
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REG_Y29
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REG_Y30
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REG_Y31
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REG_Z0
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REG_Z1
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REG_Z2
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REG_Z3
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REG_Z4
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REG_Z5
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REG_Z6
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REG_Z7
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REG_Z8
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REG_Z9
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REG_Z10
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REG_Z11
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REG_Z12
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REG_Z13
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REG_Z14
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REG_Z15
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REG_Z16
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REG_Z17
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REG_Z18
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REG_Z19
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REG_Z20
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REG_Z21
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REG_Z22
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REG_Z23
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REG_Z24
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REG_Z25
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REG_Z26
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REG_Z27
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REG_Z28
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REG_Z29
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REG_Z30
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REG_Z31
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REG_CS
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REG_SS
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REG_DS
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REG_ES
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REG_FS
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REG_GS
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REG_GDTR // global descriptor table register
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REG_IDTR // interrupt descriptor table register
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REG_LDTR // local descriptor table register
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REG_MSW // machine status word
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REG_TASK // task register
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REG_CR0
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REG_CR1
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REG_CR2
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REG_CR3
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REG_CR4
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REG_CR5
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REG_CR6
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REG_CR7
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REG_CR8
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REG_CR9
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REG_CR10
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REG_CR11
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REG_CR12
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REG_CR13
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REG_CR14
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REG_CR15
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REG_DR0
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REG_DR1
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REG_DR2
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REG_DR3
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REG_DR4
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REG_DR5
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REG_DR6
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REG_DR7
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REG_TR0
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REG_TR1
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REG_TR2
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REG_TR3
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REG_TR4
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REG_TR5
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REG_TR6
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REG_TR7
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REG_TLS
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MAXREG
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REG_CR = REG_CR0
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REG_DR = REG_DR0
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REG_TR = REG_TR0
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REGARG = -1
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REGRET = REG_AX
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FREGRET = REG_X0
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REGSP = REG_SP
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REGCTXT = REG_DX
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REGEXT = REG_R15 // compiler allocates external registers R15 down
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FREGMIN = REG_X0 + 5 // first register variable
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FREGEXT = REG_X0 + 15 // first external register
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T_TYPE = 1 << 0
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T_INDEX = 1 << 1
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T_OFFSET = 1 << 2
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T_FCONST = 1 << 3
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T_SYM = 1 << 4
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T_SCONST = 1 << 5
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T_64 = 1 << 6
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T_GOTYPE = 1 << 7
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)
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// https://www.uclibc.org/docs/psABI-x86_64.pdf, figure 3.36
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var AMD64DWARFRegisters = map[int16]int16{
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REG_AX: 0,
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REG_DX: 1,
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REG_CX: 2,
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REG_BX: 3,
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REG_SI: 4,
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REG_DI: 5,
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REG_BP: 6,
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REG_SP: 7,
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REG_R8: 8,
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REG_R9: 9,
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REG_R10: 10,
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REG_R11: 11,
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REG_R12: 12,
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REG_R13: 13,
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REG_R14: 14,
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REG_R15: 15,
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// 16 is "Return Address RA", whatever that is.
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// 17-24 vector registers (X/Y/Z).
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REG_X0: 17,
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REG_X1: 18,
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REG_X2: 19,
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REG_X3: 20,
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REG_X4: 21,
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REG_X5: 22,
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REG_X6: 23,
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REG_X7: 24,
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// 25-32 extended vector registers (X/Y/Z).
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REG_X8: 25,
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REG_X9: 26,
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REG_X10: 27,
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REG_X11: 28,
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REG_X12: 29,
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REG_X13: 30,
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REG_X14: 31,
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REG_X15: 32,
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// ST registers. %stN => FN.
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REG_F0: 33,
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REG_F1: 34,
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REG_F2: 35,
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REG_F3: 36,
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REG_F4: 37,
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REG_F5: 38,
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REG_F6: 39,
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REG_F7: 40,
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// MMX registers. %mmN => MN.
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REG_M0: 41,
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REG_M1: 42,
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REG_M2: 43,
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REG_M3: 44,
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REG_M4: 45,
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REG_M5: 46,
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REG_M6: 47,
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REG_M7: 48,
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// 48 is flags, which doesn't have a name.
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REG_ES: 50,
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REG_CS: 51,
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REG_SS: 52,
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REG_DS: 53,
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REG_FS: 54,
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REG_GS: 55,
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// 58 and 59 are {fs,gs}base, which don't have names.
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REG_TR: 62,
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REG_LDTR: 63,
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// 64-66 are mxcsr, fcw, fsw, which don't have names.
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// 67-82 upper vector registers (X/Y/Z).
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REG_X16: 67,
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REG_X17: 68,
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REG_X18: 69,
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REG_X19: 70,
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REG_X20: 71,
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REG_X21: 72,
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REG_X22: 73,
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REG_X23: 74,
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REG_X24: 75,
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REG_X25: 76,
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REG_X26: 77,
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REG_X27: 78,
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REG_X28: 79,
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REG_X29: 80,
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REG_X30: 81,
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REG_X31: 82,
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// 118-125 vector mask registers. %kN => KN.
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REG_K0: 118,
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REG_K1: 119,
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REG_K2: 120,
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REG_K3: 121,
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REG_K4: 122,
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REG_K5: 123,
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REG_K6: 124,
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REG_K7: 125,
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}
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// https://www.uclibc.org/docs/psABI-i386.pdf, table 2.14
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var X86DWARFRegisters = map[int16]int16{
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REG_AX: 0,
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REG_CX: 1,
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REG_DX: 2,
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REG_BX: 3,
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REG_SP: 4,
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REG_BP: 5,
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REG_SI: 6,
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REG_DI: 7,
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// 8 is "Return Address RA", whatever that is.
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// 9 is flags, which doesn't have a name.
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// ST registers. %stN => FN.
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REG_F0: 11,
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REG_F1: 12,
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REG_F2: 13,
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REG_F3: 14,
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REG_F4: 15,
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REG_F5: 16,
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REG_F6: 17,
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REG_F7: 18,
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// XMM registers. %xmmN => XN.
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REG_X0: 21,
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REG_X1: 22,
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REG_X2: 23,
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REG_X3: 24,
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REG_X4: 25,
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REG_X5: 26,
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REG_X6: 27,
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REG_X7: 28,
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// MMX registers. %mmN => MN.
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REG_M0: 29,
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REG_M1: 30,
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REG_M2: 31,
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REG_M3: 32,
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REG_M4: 33,
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REG_M5: 34,
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REG_M6: 35,
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REG_M7: 36,
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// 39 is mxcsr, which doesn't have a name.
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REG_ES: 40,
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REG_CS: 41,
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REG_SS: 42,
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REG_DS: 43,
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REG_FS: 44,
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REG_GS: 45,
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REG_TR: 48,
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REG_LDTR: 49,
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}
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